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LSIs for DAB
MN66710
Full-Function DAB Receiver LSI
I Overview
The MN66710 is a single-chip digital signal processing LSI for a DAB (digital audio broadcast) receiver, including OFDM demodulation, service selection, error correction, and MPEG audio decoding. The MN66710 conforms to the European DAB standard (ETS 300 401). Since the MN66710 includes an on-chip A/D converter for the IF signal input, it can be directly input the 3.072 MHz center frequency analog IF signal output from the DAB high-frequency circuit. A DAB receiver is implemented easily by combining MN66710 with a small number of additional components, in particular, 4M DRAMs for working memory, audio D/A converters, microcontrollers, and etc.
I Features
* The DAB signal-processing block is integrated on a single chip. (with external 4M DRAMs) * Supports all of DAB modes I, II, III, and IV. * Achieves a processing data rate of up to 1.536 Mbps. * Up to 4 MSC sub-channels can be selected. * MPEG audio decoder (Also supports LSF.) * Supports the standard audio D/A converter interface. * Digital audio output unit conforming EIAJ CP-1201 (External driver required.) * RDI output and dedicated audio RDI input units (For high capacity mode only.) * F-PAD and X-PAD extraction function * AIC support function provided in hardware. * Supports multiplex restructuring with no interruption of the audio signal. * TII decoding function (basic mode) * Low supply voltage: 3.3 V0.3 V * Low power: Under 500 mW
I Applications
* DAB (digital audio broadcast) receivers
Publication date: November 2001
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MN66710
I Block Diagram
RAD0 to RAD9 ADVRT ADIN ADVRB ADC I/Q Gen. OFDM De-Interleave RDT0 to RDT3 NRAMOE NRRAS NRCAS NRAMWE IQMOD NULDET FSYO MCLK24 NRST CTLDAT CTLCLK CTLLR CIRSYN DSPMON0 to DSPMON6 DSPMNEN MPUSYNC MPUMOD MPUTX MPURX MPUCLK NPADRDY TEST0 to TEST3 DAI I/F MPU I/F Audio I/F DAC I/F AFC CIR I/F Timing Gen. DSP Core (Sync/AFC/MPEG Dec.) Viterbi Dec. UEP/EEP FDAT3 FERF3 FCLK3 FWFIC FW1 to FW4 FD3EN RDIOUT RDI I/F RDIIN RDIU0 to RDIU5 SDAT SCLK SLRCK SMCK AUXDAT DAOUT
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MN66710
I Pin Arrangement
DSPMON2 DSPMON3 DSPMON4 DSPMON5 DSPMON6 DSPMNEN CIRSYN CTLLR CTLCLK CTLDAT VSS4 VDD3 FSYO NULDET AVSS ADVRB ADIN ADVRT AVDD VREF IQMOD
64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43
DSPMON1 DSPMON0 VSS3 RDT3 RDT2 RDT0 RDT1 NRAMWE NRRAS RAD9 NRCAS NRAMOE RAD8 RAD7 VDD2 VSS2 RAD0 RAD1 RAD2 RAD3 RAD6
42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22
RAD5 RAD4 FDAT3 FERF3 FCLK3 FWFIC FW1 FW2 FW3 FW4 FD3EN VDD1 VSS1 RDIOUT RDIU5 RDIU4 RDIU3 RDIIN RDIU2 RDIU1 RDIU0
Note) Do not leave any of the VDD and VSS pins open. Connect the TEST0 to TEST3 pin to VSS.
MPUSYNC NPADRDY MPUCLK MPURX MPUTX MPUMOD TEST0 TEST1 TEST2 TEST3 NRST VSS0 VDD0 MCLK24 MCLKO DAOUT AUXDAT SMCK SLRCK SCLK SDAT
(TOP VIEW)
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MN66710
I Pin Descriptions
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 Pin Name MPUSYNC NPADRDY MPUCLK MPURX MPUTX MPUMOD TEST0 TEST1 TEST2 TEST3 NRST VSS0 VDD0 MCLK24 MCLKO DAOUT AUXDAT SMCK SLRCK SCLK SDAT RDIU0 RDIU1 RDIU2 RDIIN RDIU3 RDIU4 RDIU5 RDIOUT VSS1 VDD1 FD3EN FW4 FW3 FW2 I/O O O I I O I I I I I I I O O I O O O O O O O I O O I O I O O O Descriptions Microcontroller operation reference signal PAD data ready signal Microcontroller interface data clock Microcontroller interface reception data Microcontroller interface transmission data Microcontroller interface mode Test mode setup Test mode setup Test mode setup Test mode setup Master reset input Digital system ground Digital system power supply Master clock input (24.576 MHz) Master clock oscillator circuit output SPDIF digital audio interface output Audio A/D converter serial data input Auxiliary input A/D converter connection For use with a crystal oscillator element Normally connect to VSS Normally connect to VSS Normally connect to VSS Normally connect to VSS The IC is reset when this input is set low Note Timing signal with a 24 ms period Indicates that the PAD register can be read
Audio A/D and D/A converter master clock Outputs a 256 fs clock Audio A/D and D/A converter left/right clock Audio A/D and D/A converter serial clock output Audio D/A converter serial data output Audio output D/A converter connection Auxiliary outputs for RDI expansion Auxiliary outputs for RDI expansion Auxiliary outputs for RDI expansion RDI input Auxiliary outputs for RDI expansion Auxiliary outputs for RDI expansion Auxiliary inputs for RDI expansion RDI output Digital system ground Digital system power supply General-purpose data output enable General-purpose output window 4 General-purpose output window 3 General-purpose output window 2 Output enable for FDAT3, FERF3, and FCLK3 Window for sub-channel 4 Window for sub-channel 3 Window for sub-channel 2 Normally left open Normally left open Normally left open RDI back channel (audio only) Normally left open Normally left open Normally connect to VSS For high capacity mode only
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I Pin Descriptions (continued)
Pin No. 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 Pin Name FW1 FWFIC FCLK3 FERF3 FDAT3 RAD4 RAD5 RAD6 RAD3 RAD2 RAD1 RAD0 VSS2 VDD2 RAD7 RAD8 NRAMOE NRCAS RAD9 NRRAS NRAMWE RDT1 RDT0 RDT2 RDT3 VSS3 DSPMON0 DSPMON1 DSPMON2 DSPMON3 DSPMON4 DSPMON5 DSPMON6 DSPMNEN CIRSYN CTLLR CTLCLK I/O O O O O O O O O O O O O O O O O O O O I/O I/O I/O I/O O O O O O O O I O O O Descriptions General-purpose output window 1 General-purpose output window 0 General-purpose data output clock Note Window for sub-channel 1 (audio) FIC window 1.536 MHz continuous clock
General-purpose data output error flag Flag that indicates Viterbi-corrected bits General-purpose data output data External DRAM address, bit 4 External DRAM address, bit 5 External DRAM address, bit 6 External DRAM address, bit 3 External DRAM address, bit 2 External DRAM address, bit 1 External DRAM address, bit 0 Digital system ground Digital system power supply External DRAM address, bit 7 External DRAM address, bit 8 External DRAM output enable For connecting external DRAM For connecting external DRAM For connecting external DRAM For connecting external DRAM For connecting external DRAM For connecting external DRAM For connecting external DRAM For connecting external DRAM For connecting external DRAM For connecting external DRAM
External DRAM column address strobe For connecting external DRAM External DRAM address, bit 9 External DRAM row address strobe External DRAM write enable External DRAM data, bit 1 External DRAM data, bit 0 External DRAM data, bit 2 External DRAM data, bit 3 Digital system ground DSP monitor, bit 0 DSP monitor, bit 1 DSP monitor, bit 2 DSP monitor, bit 3 DSP monitor, bit 4 DSP monitor, bit 5 DSP monitor, bit 6 DSP monitor output enable CIR display cycle signal Normally left open Normally left open Normally left open Normally left open Normally left open Normally left open Normally left open A low level disables DSP monitor output CIR monitor display trigger signal For connecting external DRAM For connecting external DRAM For connecting external DRAM For connecting external DRAM For connecting external DRAM For connecting external DRAM For connecting external DRAM
AFC/CIR D/A converter left/right clock For AFC control and CIR monitor display AFC/CIR D/A converter clock
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For AFC control and CIR monitor display 5
MN66710
I Pin Descriptions (continued)
Pin No. 73 74 75 76 77 78 79 80 81 82 83 84 Pin Name CTLDAT VSS4 VDD3 FSYO NULDET AVSS ADVRB ADIN ADVRT AVDD VREF IQMOD I/O O O I I I Descriptions AFC/CIR D/A converter data Digital system ground Digital system power supply Frame sync signal output Null symbol detection signal input Analog system ground A/D converter low side reference voltage A/D converter analog input A/D converter high side reference voltage Analog system power supply Reference supply for 5 V input pads Digital IQ generation switching input Normally connect to VDD Note For AFC control and CIR monitor display
I Electrical Characteristics
1. Absolute Maximum Ratings at Ta = 25C, VSS = 0 V Parameter Supply voltage (digital) Supply voltage (analog) 5 V reference voltage
*1
Symbol VDD AVDD VREF5 VI VI5 VI5 VO VO5 IO IO IO IO PD Tstg
Rating - 0.3 to +4.6 - 0.3 to +4.6 - 0.3 to +5.7 - 0.3 to VDD+0.3 - 0.3 to +6.0
*2 *2
Unit V V V V V V V
*2
Input pin voltage (except for the type A and type B) Input pin voltage (type A) Input pin voltage (type B) Output pin voltage (except for the type B) Output pin voltage (type B) Output current (type HL1) Output current (type HL2) Output current (type HL4) Output current (type HL8) Power dissipation Storage temperature
- 0.3 to VREF5+0.3 - 0.3 to VDD+0.3 - 0.3 to VREF5+0.3 3 6 12 24 1030 -55 to +125
V mA mA mA mA mW C
6
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MN66710
I Electrical Characteristics (continued)
1. Absolute Maximum Ratings at Ta = 25C, VSS = 0 V (continued)
Note) 1. *1 : The power supply rise and fall sequences must meet the stipulations shown below. VDD 0V t3-5 t5-3
VREF5 0 V The times t3-5 and t5-3 must be non-negative. VDD and VREF5 should change smoothly. *2 : If VDD 1.4 V: - 0.3 V to +4.6 V 2. Type A pins : RDIU5, MPURX, RDIIN, MPUCLK, MPUMOD, NULDET Type B pins : RAD9, RDT0 to RDT3, FSYO, CTLLR, DAOUT, NRCAS, NRRAS, CIRSYN, CTLCLK, CTLDAT, DSPMON0 to DSPMON6, NRAMOE, NRAMWE, DSPMNEN Type HL1 pins : FW1 to FW4, FCLK3, FDAT3, FERF3, FWFIC, DSPMON0 to DSPMON6, DSPMNEN Type HL2 pins : RDIU0 to RDIU4 Type HL4 pins : FSYO, SCLK, SDAT, SMCK, CTLLR, DAOUT, MPUTX, SLRCK, AUXDAT, CIRSYN, CTLCLK, CTLDAT, RDIOUT, MPUSYNC, NPADRDY Type HL8 pins : RAD0 to RAD9, RDT0 to RDT3, NRCAS, NRRAS, NRAMOE, NRAMWE 3. The absolute maximum ratings are limiting values under which the chip will not be destroyed. Operation is not guaranteed within these ranges. 4. External power and ground levels must be connected directly to all of the VDD and VSS pins respectively. 5. Connect the MINTEST pin to ground. 6. When used in car audio equipment, insert bypass capacitors (recommended value: 0.1 F) between VDD and VSS.
2. Recommended Operating Conditions at VSS = 0 V Parameter Supply voltage (digital) Supply voltage (analog) 5 V reference voltage Ambient temperature Input rise time Input fall time Oscillator frequency Recommended external capacitor value Symbol VDD AVDD VREF5 Ta tr tf fOSC1 CXI7 CXO7 24.576 MHz Xtal VDD = 3.3 V Built-in feedback resistor
XI XO CXO
Note) 1. Since the oscillator characteristics depend on the oscillator element itself, external capacitances, and other factors, consult the manufacturer of the oscillator element to determine the circuit constants. 2. Apply 5 V to 5 V reference voltage if 5 V inputs are used. This has no steady-state current consumption. Do not apply the 5 V if the 3.3 V is not being applied to the LSI. 3.3 V may be supplied to this pin if only a single 3.3 V power supply is used.
Conditions
Min 3.0 3.0 4.75 -30 0 0
Typ 3.3 3.3 5.0 24.576 47 47
Max 3.6 3.6 5.25 85 100 100
Unit V V V C ns ns MHz pF pF
CXI
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MN66710
I Electrical Characteristics (continued)
3. DC Characteristics at VDD = 3.0 V to 3.6 V, VREF5 = 4.75 V to 5.25 V, VSS = 0.00 V, fTEST = 24.576 MHz, Ta = -30C to +85C Parameter Operating supply current Symbol IDDO Conditions VI = VDD or VSS f = 24.576 MHz VDD = 3.3 V, outputs open Min Typ 110 Max 200 Unit mA
Oscillator circuit: MCLK24, MCLKO High-level input voltage Low-level input voltage Internal feedback resistor VIH VIL Rf7 VI = VDD or VSS VDD = 3.3 V VDD x 0.8 0 313 940 VDD VDD x 0.2 2820 V V k
CMOS level input pins: FD3EN, TEST0, TEST1, TEST2, IQMOD High-level input voltage Low-level input voltage Input leakage current VIH VIL ILI VI = VDD or VSS VDD = 3.0 V to 3.6 V VI = VDD or VSS VDD x 0.8 0 VDD x 0.2 VDD x 0.85 0 VI = VDD VI = VSS 10 VDD VDD x 0.2 5 VDD x 0.8 5 A V V A
CMOS level input pin with Schmitt trigger circuit: NRST Input threshold voltage VT+ VT- Input leakage current ILI 1.85 1.45 30 V
CMOS level input pin with built-in pull-down resistor: TEST3 High-level input voltage Low-level input voltage Pull-down resistor Input leakage current VIH VIL RIL ILI VDD VDD x 0.15 90 10 V V k A
TTL level input pins: RDIU5, MPURX, RDIIN, MPUCLK, MPUMOD, NULDET High-level input voltage Low-level input voltage Input leakage current VIH VIL ILI VI = 5.25 V or VSS IOH = -1.0 mA VI = VDD or VSS IOL = 1.0 mA VI = VDD or VSS IOH = -4.0 mA VI = VDD or VSS IOL = 4.0 mA VI = VDD or VSS 2.2 0 VDD - 0.5 5.25 0.6 10 0.4 V V A
Push-pull output pins: FW1 to FW4, FCLK3, FDAT3, FERF3, FWFIC High-level output voltage Low-level output voltage VOH VOL V V
Push-pull output pins: MPUTX, MPUSYNC, NPADRDY High-level output voltage Low-level output voltage VOH VOL VDD - 0.5 0.4 V V
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MN66710
I Electrical Characteristics (continued)
3. DC Characteristics at VDD = 3.0 V to 3.6 V, VREF5 = 4.75 V to 5.25 V, VSS = 0.00 V, fTEST = 24.576 MHz, Ta = -30C to +85C (continued) Parameter Symbol Conditions Min Typ Max Unit
Push-pull output pins: RAD0 to RAD8 High-level output voltage Low-level output voltage VOH VOL IOH = -8.0 mA VI = VDD or VSS IOL = 8.0 mA VI = VDD or VSS VDD - 0.5 0.4 V V
CMOS level I/O pins: RDIU0 to RDIU4 High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage Output leakage current VIH VIL VOH VOL ILO IOH = -2.0 mA VI = VDD or VSS IOL = 2.0 mA VI = VDD or VSS VO = High-impedance state VI = VDD or VSS VO = VDD or VSS VDD x 0.8 0 VDD - 0.5 VDD VDD x 0.2 0.4 5 V V V V A
CMOS level I/O pins: SCLK, SDAT, SMCK, SLRCK, AUXDAT, RDIOUT High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage Output leakage current VIH VIL VOH VOL ILO IOH = -4.0 mA VI = VDD or VSS IOL = 4.0 mA VI = VDD or VSS VO = High-impedance state VI = VDD or VSS VO = VDD or VSS VDD x 0.8 0 VDD - 0.5 VDD VDD x 0.2 0.4 5 V V V V A
TTL level I/O pins: DSPMON0 to DSPMON6, DSPMNEN High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage Output leakage current VIH VIL VOH VOL ILO IOH = -1.0 mA VI = VDD or VSS IOL = 1.0 mA VI = VDD or VSS VO = High-impedance state VI = 5.25 V or VSS VO = 5.25 V or VSS 2.2 0 2.4 VREF5 0.6 0.4 10 V V V V A
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MN66710
I Electrical Characteristics (continued)
3. DC Characteristics at VDD = 3.0 V to 3.6 V, VREF5 = 4.75 V to 5.25 V, VSS = 0.00 V, fTEST = 24.576 MHz, Ta = -30C to +85C (continued) Parameter Symbol Conditions Min Typ Max Unit
TTL level I/O pins: FSYO, CTLLR, DAOUT, CIRSYN, CTLCLK, CTLDAT High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage Output leakage current VIH VIL VOH VOL ILO IOH = -4.0 mA VI = VDD or VSS IOL = 4.0 mA VI = VDD or VSS VO = High-impedance state VI = 5.25 V or VSS VO = 5.25 V or VSS 2.2 0 2.4 VREF5 0.6 0.4 10 V V V V A
TTL level I/O pins: RAD9, RDT0 to RDT3, NRCAS, NRRAS, NRAMOE, NRAMWE High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage Output leakage current VIH VIL VOH VOL ILO IOH = -8.0 mA VI = VDD or VSS IOL = 8.0 mA VI = VDD or VSS VO = High-impedance state VI = 5.25 V or VSS VO = 5.25 V or VSS 2.2 0 2.4 VREF5 0.6 0.4 10 V V V V A
4. AC Characteristics at VDD = 3.0 V to 3.6 V, VREF5 = 4.75 V to 5.25 V, VSS = 0.00 V, fTEST = 24.576 MHz, Ta = -30C to +85C Parameter Clock input MCLK24 clock period MCLK24 high-level period MCLK24 low-level period Microcontroller interface
MPUCLK clock period MPUCLK high-level period MPUCLK low-level period
Symbol
Conditions
Min
Typ
Max
Unit
tMCLK tMCLKH tMCLKL
See figure 1.
36 18 15
40.69
45
ns ns ns
tMPUC tMPUCH tMPUCL
See figure 2.
4xT 72 60
ns ns ns
Note) The symbol T in the table refers to the MCLK24 period, tMCLK.
10
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MN66710
I Electrical Characteristics (continued)
4. AC Characteristics at VDD = 3.0 V to 3.6 V, VREF5 = 4.75 V to 5.25 V, VSS = 0.00 V, fTEST = 24.576 MHz, Ta = -30C to +85C (continued) Parameter Symbol Conditions Min Typ Max Unit
Microcontroller interface (continued) MPUMOD setup time MPUMOD hold time MPURX setup time MPURX hold time MPUTX delay time Write disabled period 1 Write disabled period 2 Read disabled period DRAM interface Random read/write cycle time RAS precharge time RAS pulse width CAS pulse width Row address setup time Row address hold time Column address setup time Column address hold time RAS/CAS delay time RAS column address delay time RAS hold time CAS hold time CAS/RAS precharge time OE/data input delay time Write command setup time Write command hold time Data input setup time Data input hold time Fast page mode cycle time Fast page mode precharge time tRC tRP tRAS tCAS tASR tRAH tASC tCAH tRCD tRAD tRSH tCSH tCRP tODD tWCS tWCH tDS tDH tPC tCP See figure 5. 120 37.5 75 17.5 10 17.5 10 17.5 35 17.5 35 60 37.5 20 40 15 12.5 17.5 40 15 40 80 20 40 17.5 45 25 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns tMODS tMODH tRXS tRXH tTXD tWRNG1 tWRNG2 tRDNG See figure 3,4. 0 2xT 0 2xT 6xT 2xT ns ns ns ns ns ns ns ns
4xT 8xT 4xT 8xT
Note) The symbol T in the table refers to the MCLK24 period, tMCLK.
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MN66710
I Electrical Characteristics (continued)
4. AC Characteristics at VDD = 3.0 V to 3.6 V, VREF5 = 4.75 V to 5.25 V, VSS = 0.00 V, fTEST = 24.576 MHz, Ta = -30C to +85C (continued) Parameter DRAM interface (continued) Master clock/RAS delay time Master clock/CAS delay time Master clock/address delay time Master clock/WE delay time Master clock/data input delay time Master clock/OE delay time Data output setup time Data output hold time Audio interface SMCK clock period SMCK high-level period SMCK low-level period SCLK period SCLK high-level period SCLK low-level period SCLK delay time SDAT delay time SLRCK delay time AUXDAT setup time General-purpose data outputs FCLK3 clock period FCLK3 high-level period FCLK3 low-level period FCLK3 delay time FDAT3 delay time FERF3 delay time FWFIC and FW1:4 delay time tFCLK tFCLKH tFCLKL tFCLKD tFDATD tFERFD tFWD See figure 8. 576 651.04 200 200 15.5 21.5 21 18 ns ns ns ns ns ns ns tSMCK tSMCKH tSMCKL tSCLK tSCLKH tSCLKL tSCLKD tSDATD tSLRD tAUXS See figure 7. See figure 6. 72 31 31 81.38 41 40 41 ns ns ns ns ns ns ns ns ns ns t1 t2 t3 t4 t5 t6 t7 t8 See figure 5. 7 7 27.5 7 27.5 7 0 20 32.5 32.5 57.5 32.5 57.5 30 ns ns ns ns ns ns ns ns Symbol Conditions Min Typ Max Unit
288 325.52 100 100 8.5
12
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I Electrical Characteristics (continued)
4. AC Characteristics at VDD = 3.0 V to 3.6 V, VREF5 = 4.75 V to 5.25 V, VSS = 0.00 V, fTEST = 24.576 MHz, Ta = -30C to +85C (continued) Parameter CIR/AFC Output Timing CTLCLK clock period CTLCLK high-level period CTLCLK low-level period CIRSYN delay time CTLCLK delay time CTLDAT delay time CTLLR delay time tCCLK tCCLKH tCCLKL tCIRD tCCLKD tCDATD tCLRD See figure 9. 576 200 200 651.04 241 35 35 37 ns ns ns ns ns ns ns Symbol Conditions Min Typ Max Unit
5. A/D Converter Characteristics at VDD = 3.30 V, VREF5 = 5.00 V, VSS = 0.00 V, Ta = 25C Parameter Resolution Nonlinearity error Differential nonlinearity error Symbol RES NLE1 DNLE1 fMSPCK = 24.576 MHz VRT = 2.6 V, VRB = 0.6 V fMSPCK = 24.576 MHz VRT = 2.6 V, VRB = 0.6 V Conditions Min Typ 1.5 0.5 Max 8 2.0 1.5 Unit bit LSB LSB
tMCLK tMCLKH MCLK24 Figure 1. Clock input tMCLKL
tMPUC tMPUCH MPUCLK Figure 2. Microcontroller interface (data clock) tMPUCL
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14
MPUCLK tMODH tRXH tRXS b0 b7 b6 b0 b7 b6 b0 tWRNG1 tWRNG2
MN66710
tMODS
MPUMOD
tRXH tRXS
MPURX
b7
b6
I Electrical Characteristics (continued)
MPUTX unknown
SDC00041BEM
Figure 3. Microcontroller interface (data write time)
MPUCLK tMODH tTXD tRDNG
tMODS
MPUMOD
tRXH tRXS b0
MPURX
b7
b6
MPUTX
unknown
b7
b6
b0
b7
b6
Figure 4. Microcontroller interface (data read time)
Read cycle Read cycle tRC tRP tRAS
Fast page mode early write cycle RAS only refresh cycle
NRRAS tCSH tCRP tASR tRAH row t4 tWCS tWCH column row col. col. col. col. row tCAH tASC column row row tRCD tCAS tCP tPC tRSH
t1
tRCD tRSH
I Electrical Characteristics (continued)
tCSH
NRCAS
t3
t2 tRAD
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RAD9-RAD0
row
column
NRAMWE t5 dataout tODD t6 datain datain datain datain tDH tDS dataout
RDT3-RDT0
dataout
t7 t8
NRAMOE
MCLK24
MN66710
Figure 5. DRAM interface
15
MN66710
I Electrical Characteristics (continued)
tSMCK tSMCKH SMCK Figure 6. Audio interface tSMCKL
MCLK24 tAUXS AUXDAT tSCLK tSCLKH tSCLKL
tSCLKD SCLK tSDATD SDAT tSLRD SLRCK
Figure 7. Audio output timing
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I Electrical Characteristics (continued)
MCLK24 tFCLK tFCLKH tFCLKL
tFCLKD FCLK3
tFDATD FDAT3 tFERFD FERF3 tFWD FWFIC FW1 to FW4 Figure 8. General-purpose data output
MCLK24 tCIRD
CIRSYN tCCLKD tCCLKH
tCCLK tCCLKL
CTLCLK
tCDATD
CTLDAT tCLRD CTLLR Figure 9. CIR/AFC output timing
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MN66710
I Package Dimensions (Unit: mm)
* QFP084-P-1818E (Lead-free package)
22.900.20 18.000.10 63 43
64
42
84
22
18.000.10 22.900.20
(1.00) 0.80 0.350.05
(1.00)
2.450.20
1
21
2.85 max.
(2.45)
Seating plane
0.15
0.100.10
0.150.05
1.300.20
0 to 10
18
SDC00041BEM
Request for your special attention and precautions in using the technical information and semiconductors described in this material
(1) An export permit needs to be obtained from the competent authorities of the Japanese Government if any of the products or technologies described in this material and controlled under the "Foreign Exchange and Foreign Trade Law" is to be exported or taken out of Japan. (2) The technical information described in this material is limited to showing representative characteristics and applied circuit examples of the products. It does not constitute the warranting of industrial property, the granting of relative rights, or the granting of any license. (3) The products described in this material are intended to be used for standard applications or general electronic equipment (such as office equipment, communications equipment, measuring instruments and household appliances). Consult our sales staff in advance for information on the following applications: * Special applications (such as for airplanes, aerospace, automobiles, traffic control equipment, combustion equipment, life support systems and safety devices) in which exceptional quality and reliability are required, or if the failure or malfunction of the products may directly jeopardize life or harm the human body. * Any applications other than the standard applications intended. (4) The products and product specifications described in this material are subject to change without notice for reasons of modification and/or improvement. At the final stage of your design, purchasing, or use of the products, therefore, ask for the most up-to-date Product Standards in advance to make sure that the latest specifications satisfy your requirements. (5) When designing your equipment, comply with the guaranteed values, in particular those of maximum rating, the range of operating power supply voltage and heat radiation characteristics. Otherwise, we will not be liable for any defect which may arise later in your equipment. Even when the products are used within the guaranteed values, redundant design is recommended, so that such equipment may not violate relevant laws or regulations because of the function of our products. (6) When using products for which dry packing is required, observe the conditions (including shelf life and after-unpacking standby time) agreed upon when specification sheets are individually exchanged. (7) No part of this material may be reprinted or reproduced by any means without written permission from our company.
Please read the following notes before using the datasheets
A. These materials are intended as a reference to assist customers with the selection of Panasonic semiconductor products best suited to their applications. Due to modification or other reasons, any information contained in this material, such as available product types, technical data, and so on, is subject to change without notice. Customers are advised to contact our semiconductor sales office and obtain the latest information before starting precise technical research and/or purchasing activities. B. Panasonic is endeavoring to continually improve the quality and reliability of these materials but there is always the possibility that further rectifications will be required in the future. Therefore, Panasonic will not assume any liability for any damages arising from any errors etc. that may appear in this material. C. These materials are solely intended for a customer's individual use. Therefore, without the prior written approval of Panasonic, any other use such as reproducing, selling, or distributing this material to a third party, via the Internet or in any other way, is prohibited.
2001 MAR

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